1. Field of the Invention
The present invention is related to a cyclic redundancy check (CRC) generator and checker and, more particularly, to a CRC generator using parallel look-ahead logic to generate CRC bits at high speed.
2. Description of the Related Art
Many forms of digital data transfer use cyclic redundancy (CRC) codes for error detection. Using 16 CRC bits for each frame of data, a frame may contain thousands of bits and yet all of the following types of errors can be detected: single bit and double-bit errors, any odd number of errors and many burst errors including all which have a length of less than 16 bits, provided certain rules are followed in generating the CRC bits.
The CRC bits are generated by performing manipulations on the data which are equivalent to dividing the data by a generator polynomial using modulo 2 arithmetic. Error detection using CRC bits is well known in the art and several standard generator polynomials have been defined. For example, the Consultative Committee for International Telegraph and Telephone (CCITT) has established a standard using the generator polynomial X.sup.16 +X.sup.12 +X.sup.5 +1. This CRC standard has been adopted by the Society of Automotive Engineers (SAE) Avionics Systems 2 section in their High Speed Ring Bus (HSRB) standard AS4074.2. The HSRB standard includes operation at 80 MHz with the data frames and CRC bits or frame check sequences (FCSs) concatenated.
No single conventional CRC generator is capable of operating at 80 MHz to produce concatenated frames and FCSs. In order to obtain data in the format required by SAE-HSRB, a conventional CRC generator would have to operate at a much higher clock speed or two overlapped CRC generators would have to be used.